Point Defect Aggregation in Silicon Under Thermoelastic Stresses in Silicon-On-Insulator (SOI) Wafers

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Point Defect Aggregation Under Thermoelastic Stresses in Silicon-On-Insulator (SOI) Wafers

Ed Wijaranakula, Ph.D.
Chief Technology Officer, Infotix Systems, Inc. - June 23, 2002

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It is recognized that a good understanding of point defect aggregation in silicon is important for the development of the nanoelectronic manufacturing process because point defect aggregation is an initial step of the total crystallographic defect generation process.

The aggregation of vacancies during Czochralski (Cz) silicon crystal growth leads to the formation of nanometer-size voids which degrade the integrity of thin gate oxide[1]-[3]. Chaundhry et al [4] observed smaller sizes and densities of the dislocation loops induced by ion implantation in the compressive regions underneath the nitride film below the buffer oxide film and suggested that the compressive stress field forces an increase in the equilibrium concentration of vacancies which in turn causes the dislocation loops to shrink.

Semiconductor companies like Intel (NASDAQ: INTC) and Advanced Microdevices (NYSE:AMD) are planning to use SiGe strained silicon, nitride-induced film stresses, and silicon-on-insulator (SOI) in their high-volume nanoelectronic processes to improve chip performance including transistor operation speed and power consumption. Because nanodefects affect chip performance and yield, the number of good chips per finished wafer, thermoelastic stresses resulting from SIGe strained silicon or the thermal expansion coefficient misfit between the silicon superficial layer and buried oxide (BOX) in silicon-on-insulator (SOI) structure could become an increasingly important issue with respect to defect generation during nanoelectronic device processing.

Figure 1 shows plots of σ_zz and σ_rr distributions as a function of distance from the SOI surface at room temperature (RT) and 650°C where σ_zz is the principle stress in the direction perpendicular to the SOI surface and σ_rr is the principle stress in the radial direction. The results were calculated using the finite element analysis based upon the SOI layer thickness of 100 nm and the buried oxide thickness of 500 nm. At room temperature, the silicon-oxide interface is highly compressed while σ_zzin the silicon substrate beyond 100 nm from the buried oxide layer is negligibly small. In the SOI structure, the radial stresses σ_rr is tensile and probably have little or no impact on defect generation. At 650°C, the compressive stress level is reduced as the thermal expansion misfit between silicon and silicon oxide decreases.

Figure 2 shows a cross-sectional TEM micrograph of typical rod-like defects in the silicon SOI top layer after a 120-hour annealing at 650°C in nitrogen ambient. Extended annealing at this temperature is known to induce heavy oxygen precipitation and silicon interstitial supersaturation in silicon. Similar rod-like defects are also observed in the silicon regions underneath the buried oxide.

FIGURE 1

FIGURE 2

Figure 3 shows a high-resolution electron micrograph (HREM) of the rod-like defects in the regions underneath the buried oxide layer. The morphology of rod-like defects are identical to

the {113}-interstitial type defects generated in Cz silicon as a result of an aggregation of excess silicon interstitials emitted from oxide precipitates during an extended annealing, typically more than several hours.[6]

To be consistent with Chaudhry et al's model [4] where the compressive stress field forces an increase in the equilibrium concentration of vacancies, we suggest that the compressive stress decreases the equilibrium concentration of silicon interstitials during annealing at 650°C. Consequently, the silicon interstitial concentration in the SOI layer and the regions underneath the buried oxide layer will be supersaturated as the result of compressive stress fields.

FIGURE 3

By comparing the rod-like defect formation with the simulated thermoelastic stress distributions in the silicon-on-insulator structure, we suggest that the rod-like defect formation occurs preferably in silicon under the compressive stress field. We suggest that the compressive stress field decreases the equilibrium concentration of silicon interstitials which in turn leads to an aggregation of the interstitial-type defects.

REFERENCES

[1] W. Wijaranakula, K. Takano, and H. Yamagishi, in High Purity Silicon, C.L. Claeys, P. Rai-Choudhury, P. Stallhofer, and J.E. Maurtis, Editors (The Electrochemical Society Softbound Proceeding Series, Pennington, NJ, 1996) p. 180.
[2] E. Dornberger, J. Esfandyari, D. Gräf, U. Lambert, J. Vanhellemont, F. Dupret, and W. von Ammon, in Meeting Abstracts (The Electrochemical Society, Vol.97-2, Pennington, NJ, 1997) p. 2249.
[3] M. Itsumi, in Defects in Electronic Materials II, J. Michel, T. Kennedy, K. Wada, and K. Thonke, Editors (Materials Research Society, Pittsburgh, PA, 1997) p. 95.
[4] S. Chaudhry and M.E. Law, J.Appl.Phys., 82, 1138(1997).
[5] R. Egloff, T. Letavic, B. Greenberg, and H. Baumgart, in Semiconductor Wafer Bonding: Science, Technology and Application, C.E. Hunt, H. Baumgart, S.S. Iyer, T. Abe and U.M. Gősele, Editors (The Electrochemical Society Softbound Proceeding Series, Pennington, NJ, 1995) p.236.
[6] K. Tempelhoff, B. Hahn and R. Gleichmann, in Semiconductor Silicon 1981, H.R Huff, R. J. Kriegler and Y. Takeishi Editors (The Electrochemical Society Softbound Proceeding Series, Pennington, NJ, 1981) p.244.

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About the Author: Dr. Ed Wijaranakula is presently the Chief Technology Officer at Infotix Systems, Inc. Prior to Infotix Systems, he has worked with Intel, Hewlett-Packard, Micron, Motorola and Texas Instruments and has held senior as well as managerial positions in semiconductor manufacturing companies. He has published over 80 technical papers and holds more than 12 U.S. and foreign patents.