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Patents:
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[1]
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Silicon
and Oxygen Ion Co-Implantation For Metallic Gettering in
Epitaxial Wafers, W. Wijaranakula, J. Ravi and N.
Tate, U.S. Patent
No. 6,569,749, May 27, 2003.
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[2]
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Heat Shield Assembly and Method for Improving Mechanical Strength of the Neck section of CZ Silicon Crystal,
W. Wijaranakula, and A.
Tamura, Japanese
Patent No. 3,294,856, April
5, 2002.
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[3]
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Silicon
and Oxygen Ion Co-Implantation For Metallic Gettering in
Epitaxial Wafers, W.
Wijaranakula, J. Ravi and N. Tate, U.S.
Patent No. 6,022,793, Febuary 8, 2000.
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[4]
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Method
for Manufacturing Calibration Wafers having a Precise
Depth of the Microdefect-Free Layer, W.
Wijaranakula, U.S.
Patent No. 5,961,713, October 05, 1999.
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[5]
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Silicon
and Oxygen Ion Co-Implantation For Metallic Gettering
in Epitaxial Wafers, W. Wijaranakula, J. Ravi and
N. Tate, W.I.P.O.
Patent No. WO9,921,222A1, April
29, 1999.
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[6]
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Method
for Improving Mechanical Strength of the Neck Section of
Czochralski Silicon Crystal, W. Wijaranakula, and A.
Tamura, U.S.
Patent No. 5,865,887,
February 2, 1999.
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[7]
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Apparatus
for Improving Mechanical Strength of the Neck Section of
Czochralski Silicon Crystal, W. Wijaranakula, and A.
Tamura, U.S.
Patent No. 5,827,367,
October 27, 1998.
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[8]
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Apparatus
for Improving Mechanical Strength of the Neck Section of
Czochralski Silicon Crystal,
W. Wijaranakula, and A.
Tamura, W.I.P.O.
Patent No. 9,811,280A1,
March 19, 1998.
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[9]
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Method
for Producing Semiconductor Wafers with Low Light
Scattering Anomalies,
W. Wijaranakula, S. Archer,
and D. Gupta, U.S.
Patent No. 5,629,216, May 13, 1997.
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[10]
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Method
for Manufacturing a Calibration Wafer Having a
Microdefect-Free Layer of a Precisely Predetermined
Depth,
W. Wijaranakula, U.S.
Patent No. 5,611,855, March 18, 1997.
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[11]
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Method
for Forming Epitaxial Semiconductor Wafer for CMOS
Integrated Circuits,
K. Mitani and W. Wijaranakula, U.S.
Patent No. 5,702,973, December 30, 1997.
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[12]
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Manufacture
of Calibration Wafer Having a Microdefect-Free Layer of
a Precisely Predetermined Depth
and Calibration
Wafer, W.
Wijaranakula, Japanese
Patent No. JP8,298,233A2, November 12, 1996.
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[13]
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Epitaxial
Silicon Wafer for CMOS Integrated Circuits,
K.
Mitani and W. Wijaranakula, W.I.P.O.
Patent No 9,425,988A1,
November 10, 1994.
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[14]
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Epitaxial
Silicon Wafer for CMOS Integrated Circuits,
K.
Mitani and W. Wijaranakula, U.S.
Patent No. 5,306,939, April 26, 1994.
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